This invention relates to the field of logic analyzers. More particularly, this invention relates to logic analyzers that are switched between a plurality of trigger states forming a sequence of trigger states.
It is known to provide logic analyzers which switch between a plurality of trigger states, each trigger state corresponding to a state in which one or more hardware signals of the hardware circuitry under test are matched against predetermined values to identify predetermined conditions/states of the hardware circuitry. A problem which arises is that as the number of trigger states increases there is a significant increase in the control overhead associated with providing the ability to flexibly move between different combinations of trigger states as may be required to perform logic analysis operations. Logic analyzers are typically provided for the purposes of debugging hardware circuitry and accordingly it is desirable that they have a high degree of flexibility in the trigger states they support and their ability to examine and match hardware signals. Providing support for such a high degree of flexibility increases the overhead associated with the logic analyzer, both in terms of circuit area and power consumption. As the logic analyzer is primarily aimed for use during debugging, and not during functional operation, it is desirable that the overhead associated with the logic analyzer be kept low.